U.2

The U.2 edge connector on Blade 3 carries four lanes of PCIe 3.0, a SATA 3.0 channel and a 12 V power input.

It is used by:

• the M.2 NVMe adapter included with the Blade 3 Case
• the Blade 3 Breakout Board, which brings out 12 V power input, PCIe for clustering, and SATA

For powering the board through this connector, see Power Supply.

After you install an NVMe SSD, run lsblk on Blade 3 and check that it lists an nvme0n1 disk.

Specifications

• 68-pin U.2 edge connector
• PCIe 3.0 x4
• SATA 3.0
• 12 V power input, 12 V at 3 A, on pins P13 to P15

Pin Assignments

Pin#	PinName	PinType	Input/Output	Signal Description
E1	PCIE30_REFCLKP_SLOT	LVDS	Output	RC PCIe30 differential clock Positive
E2	PCIE30_REFCLKN_SLOT	LVDS	Output	RC PCIe30 differential clock Negative
E3	VCC_3V3_S0	Power	Output	Power supply for IO
E4	PCIE30X4_CLKREQN_M1_L	signal	Output	DM PCIe30 Channel Reference clock request
E5	PCIE30X4_PERSTN_M1_L	signal	Input	DM PCIe30 Channel reset
E6	PCIE30X4_CLKREQN_M3	signal	Input	RC PCIe30 Channel Reference clock request
E7	PCIE30_PORT1_REFCLKP	LVDS	Input	DM PCIe30 differential clock Positive
E8	PCIE30_PORT1_REFCLKN	LVDS	Input	DM PCIe30 differential clock Negative
E9	GND	Power	NA	Power and signal reference ground
E10	PCIE30_PORT1_TX2P	LVDS	Output	DM PCIe30 transmit differential Positive
E11	PCIE30_PORT1_TX2N	LVDS	Output	DM PCIe30 transmit differential Negative
E12	GND	Power	NA	Power and signal reference ground
E13	PCIE30_PORT1_RX2N	LVDS	Input	DM PCIe30 receive differential Negative
E14	PCIE30_PORT1_RX2P	LVDS	Input	DM PCIe30 receive differential Positive
E15	GND	Power	NA	Power and signal reference ground
E16	NC	float	NA	Not connected to this pin
E17	PCIE30_PORT0_RX1P	LVDS	Input	RC PCIe30 receive differential Positive
E18	PCIE30_PORT0_RX1N	LVDS	Input	RC PCIe30 receive differential Negative
E19	GND	Power	NA	Power and signal reference ground
E20	PCIE30_PORT0_TX1N	LVDS	Output	RC PCIe30 transmit differential Negative
E21	PCIE30_PORT0_TX1P	LVDS	Output	RC PCIe30 transmit differential Positive
E22	GND	Power	NA	Power and signal reference ground
E23	I2C4_SCL_M0	signal	Output	I2C4 Bus clock
E24	I2C4_SDA_M0	signal	BI	I2C4 Bus data
E25	DUALPORT_EN#	signal	Output	GPIO for Enable dual port, default low
P1	PCIE30X4_WAKEN_M1_L	signal	Output	DM PCIE30 Wake up signal from RC
P2	PCIE30X4_WAKEN_M3	signal	Input	RC PCIE30 Wake up signal from DM
P3	PWRDIS	signal	Output	GPIO for power disable to device
P4	IFDET	signal	Input	GPIO for detect interface of device
P5	GND	Power	NA	Power and signal reference ground
P6	GND	Power	NA	Power and signal reference ground
P7	NC	float	NA	Not connected to this pin
P8	NC	float	NA	Not connected to this pin
P9	NC	float	NA	Not connected to this pin
P10	PRSNT#	signal	Input	GPIO for detect device if present
P11	ACTIVITY#	signal	Input	GPIO for detect device if activity
P12	GND	Power	NA	Power and signal reference ground
P13	U2_12V	Power	Input	Power supply for blade3, input 12V
P14	U2_12V	Power	Input	Power supply for blade3, input 12V
P15	U2_12V	Power	Input	Power supply for blade3, input 12V
S1	GND	Power	NA	Power and signal reference ground
S2	SATA0_TXP	LVDS	Output	SATA30 Port0 transmit differential Positive
S3	SATA0_TXN	LVDS	Output	SATA30 Port0 transmit differential Negative
S4	GND	Power	NA	Power and signal reference ground
S5	SATA0_RXN	LVDS	Input	SATA30 Port0 receive differential Negative
S6	SATA0_RXP	LVDS	Input	SATA30 Port0 receive differential Positive
S7	GND	Power	NA	Power and signal reference ground
S8	GND	Power	NA	Power and signal reference ground
S9	NC	float	NA	Not connected to this pin
S10	NC	float	NA	Not connected to this pin
S11	GND	Power	NA	Power and signal reference ground
S12	NC	float	NA	Not connected to this pin
S13	NC	float	NA	Not connected to this pin
S14	GND	Power	NA	Power and signal reference ground
S15	PCIE30X4_PERSTN_M3	signal	Output	RC PCIe30 Channel reset
S16	GND	Power	NA	Power and signal reference ground
S17	PCIE30_PORT1_TX3P	LVDS	Output	DM PCIe30 transmit differential Positive
S18	PCIE30_PORT1_TX3N	LVDS	Output	DM PCIe30 transmit differential Negative
S19	GND	Power	NA	Power and signal reference ground
S20	PCIE30_PORT1_RX3N	LVDS	Input	DM PCIe30 receive differential Negative
S21	PCIE30_PORT1_RX3P	LVDS	Input	DM PCIe30 receive differential Positive
S22	GND	Power	NA	Power and signal reference ground
S23	PCIE30_PORT0_RX0P	LVDS	Input	RC PCIe30 receive differential Positive
S24	PCIE30_PORT0_RX0N	LVDS	Input	RC PCIe30 receive differential Negative
S25	GND	Power	NA	Power and signal reference ground
S26	PCIE30_PORT0_TX0N	LVDS	Output	RC PCIe30 transmit differential Negative
S27	PCIE30_PORT0_TX0P	LVDS	Output	RC PCIe30 transmit differential Positive
S28	GND	Power	NA	Power and signal reference ground